Microprocessors Lecture 5
It is often useful to think about the sequence of events that
occur when an instruction is being executed by the processor.
Obviously the first thing that must happen when any instruction
is to be executed is that the first byte of the instruction must
be read into instruction register. This is known as the
Instruction Fetch Cycle.
This also takes place in a single clock cycle - so the whole
instruction requires two clock cycles,
- The contents of the Program Counter is output on the address bus.
- The contents of that memory location, the instruction code,
is returned on the data bus
- The instruction code is loaded into the Instruction Register.
- The Program Counter is incremented by one.
In the case of the 6809 all this takes place in one clock cycle,
typically 1 microsecond depending on the clock speed.
What happens next depends entirely on the particular instruction
code. Suppose the code is 86 'Load Acc A using immediate
- Program Counter -> Address Bus
- Contents of Memory Location -> Data Bus
- Data Bus -> Acc A
- Program Counter + 1 -> Program Counter
Suppose the instruction code is B6 00 02 'Load Acc A using
extended addressing from location 0002' and the instruction
starts at 0025.
Address Bus Data Bus
1) [PC] Address Bus 0025 ??
2)  Data Bus 0025 B6
3) Data Bus Instruction Register 0025 B6
4) PC + 1 PC
5) [PC] Address Bus 0026 ??
6)  Data Bus 0026 00
7) Data Bus TempH 0026 00
8) PC + 1 PC
9) [PC] Address Bus 0027 ??
10)  Data Bus 0027 02
11) Data Bus TempL 0027 02
12) PC + 1 PC
Cycle 4 Nothing
13) [Temp] Address Bus 0002 ??
14)  Data Bus 0002 93
15) Data Bus Acc A 0002 93
When they are broken down like this you can see how similar each
of the cycles really is. In this particular case each cycle is a
memory read cycle. The timing of such a memory read is obviously
important and requires the use of clock and control signals
generated by the processor.
The processor chip has an oscillator which is controlled by an
8-bit Motorola microprocessors require a non-overlapping clock
to drive the internal circuits.
There is a range of frequencies over which the
processor will work, with an upper limit dictated by all the
devices in the system and propagation delays on the buses.
There is also, surprisingly, a lower limit because the processor
uses dynamic registers which lose data if it is not refreshed
within a given length of time.
The processor outputs two clock signals Q and E. Q is used to
indicate that a valid address is present on the address bus and E
is used to indicate when a memory or interface device can put
data on the data bus in a read cycle. A control signal R/W is
used to indicate whether a read or write cycle is in progress.
The following diagram shows a memory read cycle.
A similar timing diagram can be drawn for a memory write
operation which would occur during an instruction such as 'Store
Acc B in location FE02' F7 FE 02.
A graphical display of microprocessor operations and bus cycles
was developed as a student project in 1995.
Although this display is based on an Intel processor, it will
still be of interest.
The software is only available on the Departmental Server.
Go to \APPS\MICROS and run pptview.exe.
The following programs can then be run as a screen show:
The information above has not been completely tested, and
no guarantee is given.
- program1.ppt - FETCH and EXECUTE cycle
- program2.ppt - STORE data in memory
- program3.ppt - ADD two numbers (held in memory)
- program4.ppt - as above
- program5.ppt - SUBTRACT operation, uses NEG flag
- program6.ppt - MULTIPLICATION by repeated addition
MICROPRO team: D Patel, GIO, S King, G Shaw, V A Warnes, T H Lee
H P Tay, A Demola
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