Microprocessors Lecture 8

VIA control registers and handshaking

The VIA has a total of 16 registers, some of which we have already looked at. Some of the others are concerned with the control lines we looked at before and others with features we have not yet considered.

6522 VIA
AddressNameFunction
0 ORB/INB Output or input register B
1 ORA/INA Output or input register A
2 DDRB Data direction register B
3 DDRA Data direction register A
4 (write)
4 (read)
T1L-L
T1C-L
Write to Tl latch
Read from Tl counter
5 (write)
5 (read)
T1L-H
T1C-H
Write to Tl latch & load counter
Read from Tl counter
6 (write)
6 (read)
T1L-L
T1L-L
Write to Tl latch (same as 4)
Read from latch
7 (write)
7 (read)
T1L-H
T1L-H
Write to Tl latch (no counter load)
Read from latch
8 (write)
8 (read)
T2L-L
T2C-L
Write to T2 latch
Read from T2 counter
9 (write)
9 (read)
T2L-H
T2C-H
Write to T2 latch & load counter
Read from T2 counter
A SR Shift register Serial input/output
B ACR Auxiliary control register
C PCR Peripheral control register
D IFR Interrupt flag register
E IER Interrupt enable register
F ORA Output register A (no effect on CA2)

The control and flag registers are important to the labwork. The serial interface will be looked at in more detail later and the timer functions will very briefly looked at.

Timer Functions

The timer in a computer system is simply a counter - usually sixteen or more bits to provide a reasonable range. This can be used in two main ways - counting up to record a number of events e.g. number of people entering through a turnstile or counting down to measure an elapsed time. In addition to the counting direction the source of clock pulses is different - in the first case the clock comes from an external sensor and in the second the system clock. The way the data is used is also different - in the first case the processor simply reads the count whenever it requires the data and in the second the processor needs to know when the count reaches zero, this is done using interrupts which we will look at later.

By adding a second timer and a simple gate we enable the processor to measure frequency. Timer 2 is used to generate a signal of a defined period, say 1 ms (=1000 counts). This is anded with the unknown frequency signal to generate an input to the first timer T1. The number of counts in the fixed period is a measure of the frequency. Thus the processor can easily decode a frequency modulated signal.

The same arrangement with signals reversed can be used to measure the width of a pulse. The pulse of unknown width is fed into the and gate with a clock of fixed frequency (system clock usually). The count within the period of the pulse gives a measure of the pulse width.

Adding a flip/flop and a latch, the contents of which automatically loads into the counter (in count down mode) enables a regular time signal to be generated. This may be used by the processor e.g. to update its own real-time clock (e.g. every second) or the signal may be output to external equipment (e.g. to generate a pulse train to sound a signal). The second counter may be used to switch the pulse train on and off so we have an easy way of generating tone bursts.

There are special counter-timer chips which incorporate all these and other functions. The timers on the VIA a somewhat more limited and do not do all this. Nevertheless they are a useful extension to the interface functions. They are functionally separate from the normal 8 bit interface A and B.

Control registers

The Peripheral Control Register is the most important one as it sets up the way in which the two control lines of each interface are used. It is organised as follows:-

Peripheral Control Register
Bit7654 3210
FunctionCB2 ControlCB1CA2 ControlCA1

Bits 0 and 4

The control lines CA1 and CB1 are both input signals. They are of course looking for transistions or changes in the input signal to indicate when data is available or when data has been accepted. These control bits determine whether they look for a 0 to 1 transition or a 1 to 0 transition.
                    0 = 1 to 0 transition (negative edge)
                    1 = 0 to 1 transition (positive edge)
When the appropriate transition is detected a flag in the interrupt flag register is set.

Bits 1 to 3

The control line CA2 can be used as an additional input, or more normally, as an ouput. Bit 3 determines whether it is an input or an output.
                    0 = Input
                    1 = Output

Input mode (bit 3 = 0)

Bit 2 determines which transition is detected.
                    0 = 1 to 0 transition
                    1 = 0 to 1 transition
Bit 1 determines what clears the interrupt flag.
                    0 = Cleared by read or write on ORA/INA
                    1 = Cleared by other transition (check)

Output mode (bit 3 = 1)

Bit 2 determines whether automatic handshaking is used.
                    0 = Automatic handshaking
                    1 = Programmed output

Automatic Handshaking (bit 2 = 0)

Bit 1 determines the type of output
                    0 = Normal handshake
                         CA2 goes low on read or write on INA/ORA
                         CA2 goes high on active transition on CA1
                    1 = Pulse handshake
                         CA2 goes low on read or write on INA/OPA
                         CA2 goes high one cycle later

Programmed Output (bit 2 = 1)

Bit 1 determines the state of CA2
                    0 = CA2 is 0
                    1 = CA2 is 1

Bits 5 to 7

Control line CB2 can also be used as an input or an output. If the shift register function is enabled by the ACR then CB2 is used to input or output the data (check). If the shift register is disabled then bits 5 to 7 control the output in much the same way as CA2 is controlled except that CB2 goes low on read or write on INB/ORB and goes high on an active transition on CB1.

The Auxiliary Control Register provides control of the shift register and timers and an additional feature on the data registers when used for input.

Auxiliary Control Register
Bit7654 3210
FunctionT1 ControlT2SR ControlPBLPAL

Bits 0 and 1 allow latching of the input data for situations where data is only available for a very short time and the processor might miss it.

When the bit is 0 then no latching occurs - when the bit is 1 then data is latched by the active transition on CA1 (or CB1). The data remains in the latch and can be read by the processor until the appropriate interrrupt flag is cleared.

Interrupt flag register

This is a read only flag register which is used to indicate when certain events have occurred. Each bit corresponds to different event.

Interrupt Flag Register
Bit7654 3210
FlagIRQT1T2CB1CB2SRCA1CA2

It is usually obvious what sets one of these flags but we also need to know what clears the flag.

IFR Flags
FlagSet byCleared by
CA2
CA1
SR
CB2
CB1
T2
TI
IRQ
Active transition on CA2
Active transition on CA1
Completion of 8 shifts
Active transition on CB2
Active transition on CB1
Time-out of Timer 2
Time-out of Timer 1
Any flag =1
Read or write on ORA
Read or write on ORA
Read or write on SR
Read or write on ORB/INB
Read or write on ORB/INB
Read T2 counter or Write T2 latch
Read Tl counter or Write Tl latch
No flag = 1

The IRQ flag can be used to detect whether any of the flags is set. This can be important when using interrupts as we shall see. When an interrupt occurs the processor will have to identify the source. Loading the IFR and branching if minus will indicate whether or not it was the VIA.

Interrupt Enable Register

This register has one bit to correspond with each of the above flags 0 to 6. When the corresponding bit is a one then setting the flag causes the interrupt request output of the VIA to go to one thus causing an interrupt to be transmitted to the processor. If the bit is zero the no interrupt is sent.

Interrupt Enable Register
Bit7654 3210
Flag1=set
0=clear
T1T2CB1CB2SRCA1CA2

Since it is frequently necessary to enable and disable interrupts selectively a special mechanism is used to write into this register. A 1 is used in the appropriate position to indicate we wish to change a value, the required value is given in bit 7.

Thus

Thus:						7 6 5 4 3 2 1 0  IER
	 writing $81 sets   bit 0 to 1		1 0 0 0 0 0 0 1	= 81
         writing $01 resets bit 0 to 0		0 0 0 0 0 0 0 1	= 01
					value --^	      ^
					      affected bit ___|
None of the other bits is affected.
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