Microprocessors Lecture 12

Serial Interfaces

Serial interface chips are commonly called ACIAs (Asynchronous Communications Interface Adapter) or UARTs (Universal Asynchronous Receiver/Transmitter).

An ACIA contains the hardware to interface RS232 signals to the microprocessor. Since true RS232 signals are not TTL-compatible, buffers are used to bring these into TTL/CMOS levels.

The ACIA also provides error checking and synchronisation functions.

6850 ACIA

The 6850 is commonly used with Motorola microprocessors. It contains 4 registers:
	Tx data register
	Control register
	Status register
	Rx data register
but has only one register select line (i.e. 2 addresses only). This is because the first two registers are WRITE-only and the last two registers are READ-only.

In passing, note that normal instructions such as INC, DEC and SHIFT will not work with this kind of register usage since when you read or write, you are accessing a different register. Only LOAD and STORE instructions are valid for the registers above.

There is no RESET signal on the 6850. A Master Reset command has to be given to the Control Register.


A WRITE to the Tx Data Register initiates the sending of a serial character. Remember that the 6809 can write to a register in a few microseconds. It will take the ACIA around 1 ms to transmit that character at 9600 baud. So new characters should not be written to the ACIA until the precious character has been transmitted.

The end of transmission of a character can be detected by a bit in the Status Register, SR1 which is otherwise called TRDE - Transmit Data Register Empty.

Once a character has been moved from the Tx Data Register to the ACIA's Tx shift register, the TDRE flag is cleared. So another character can be queued whilst one is being transmitted.


When a character has been received (i.e. the last bit has been copied into the Rx shift register) then the RDRF (Receive Data Register Ready) flag (SR0) is set.

When the Rx Data Register is read, then the RDRF flag is automatically cleared, although the data remains in the register until overwritten by a new received character.


Setting of the TDRE and RDRE flags may cause interrupts, if the Control Register is so programmed.

Control Register

76543 210
set data word
Clock divider /
Master Reset

A write to CR1,0 of '11' causes a Master Reset which clears all registers (except SR bit 3).

The number of bits, parity selection and number of STOP bits are selected by CR2,3,4.

CR5,6 set the Tx interrupt options and CR7 sets the Rx interrupt option.

Status Register

76543 210

DCD indicates when a modem carrier is present. This signal is output by the modem.
CTS is an input to the ACIA which inhibits the transmission of new data.
FE is set if a framing error has occurred. This means that an expected STOP bit was not received.
OVRN is set if an overrun error occurred. This means that a new character was received in the Rx data register before the previous character was read by the microprocessor. Data is lost in such circumstances.
PE shows that a Parity error occurred.
IRQ shows if the 6850 is sending an interrupt signal. This flag is cleared when the Control Register is read.

These flags are automatically reset when the next character arrives or when data is read from the 6850.

RTS is generated by the ACIA when the Rx shift register is full and the data has not been read by the microprocessor. This signal may be used to prevent a remote modem from transmitting further data.

Xon/Xoff is a software protocol which tells a remote system to stop sending data. This can be used in place of RTS/CTS hardware signals. However, owing to the time taken to transmit the Xoff character itself, the receiver must have some buffering capability.
Xoff may be sent from the keyboard by typing CTRL-S and Xon by typing CTRL-Q.

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